An approach to the Verilog-based system for medical image enhancement

Abstract

This paper presents a direct implementation and improvement of the real-time configurable system for image enhancement using Verilog Hardware Description Language and reconfigurable architecture (field programmable gate array). New series of filters are developed at the hardware level for image processing (edges detection, sharpen operation, enhance contrast operation and brightness-adjustment), in order to improve the quality of images and to assist in diagnosis the medical specialists. For verification and simulation of the Verilog-based system for image enhancement was used ISIM Simulator, a component of the ISE Design Suite program, from Xilinx. Using Hardware Description Languages for image processing is a quite new approach extending the field of digital design on reconfigurable circuits to digital image processing using VLSI technologies. Describing the image enhancement techniques using Verilog HDL enables rapid prototyping of these complex algorithms offering the direct possibility of FPGA implementation.