An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency

Abstract

A new pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) structure without residue amplifier and timing-interleaving is presented in this brief. Two redistribution digital-to-analog converters (DACs) and comparators are adopted in two stages, with $\mbox{DAC}_1$ for most significant bit (MSB) comparisons and $\mbox{DAC}_2$ for least significant bit (LSB) comparisons. The previous sampled signal is transferred from $\mbox{DAC}_1$ to $\mbox{DAC}_2$ through charge sharing so that previous LSB conversions can operate simultaneously with the next sample and MSB conversions, which increases the conversion speed. With a 0.5 scale factor between two stages and multicomparator offsets, offset calibration has to be obtained to eliminate offset nonlinearity. The number of conversion cycles required by the proposed design is only 6 and sampling requires no extra time, which is 3 cycles fewer than traditional SAR ADC. The behavioral model of the 8b proposed design proves the performance stability with parasitic capacitance variation, capacitor mismatch, offset, and noise errors. An 8b prototype is designed in a 65-nm CMOS technology. The supply voltage is 1.2 V, with a 500-MS/s sampling rate. The circuit simulation results achieve 7.49b ENOB with 1.53-mW power consumption. The simulated FoM is 17 fJ/conv.