Abstract
Traditionally, each time a new Finite Impulse Response (FIR) filter is required to design, a new algorithm have to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. An Arithmetic Logic Unit (ALU) based universal FIR filter suitable for implementation in Field Programmable Gate Arrays (FPGA) is proposed in this paper. Rather than multiplier-accumulator based architecture used in conventional FIR, the proposed ALU architecture implements FIR functions by using accumulators and shift-registers controlled by the instructions of ROM. Furthermore, TDMA (Time Division Multiplexing Access) technique is employed to reduce chip size. In a case study, a 64-tap FIR filter is designed by the proposed architecture.
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