Abstract
An Alternative Modeling Methodology for Interconnects used in High-Speed CMOS Integrated Circuits In this paper, an alternative modeling methodology for on-chip interconnects used in the high-speed Systems on Chip is proposed. The methodology is developed from S-parameter measurements of on-chip microstrip lines, fabricated on a silicon substrate using a 0.35 μm Complementary Metal-Oxide-Semiconductor Technology, in order to determine effective circuit models and frequency dependent parameters used to represent the delay and losses associated with interconnection lines. An equation that allows to analytically determining the optimum number of sections for an RLC distributed equivalent model to accurately represent an interconnection line within specific frequency ranges is derived. The modeling methodology was applied to interconnection lines of several lengths, and up to 35 GHz obtaining good simulationexperiment correlations.
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