An algorithm for functional verification of digital ECL circuits

Abstract

In recent years, silicon bipolar junction transistors (BJT) have been scaled down significantly with improved switching characteristics. Consequently, emitter-coupled logic (ECL) circuits have reduced power consumption while maintaining their speed advantage over other circuit technologies. The development of very large scale ECL circuits requires advanced computer-aided design tools. In this paper, we present a new computationally efficient algorithm for functional verification of a broad class of digital ECL circuits. The functional verification algorithm uses the transistor level circuit description to calculate steady-state device currents and node voltages of switching subcircuits. Voltage regulators are identified automatically for electrical simulation. A simplified Ebers-Moll BJT model is used to calculate current sharing in emitter-coupled transistors analytically and to detect design errors such as deep transistor saturation, excessive emitter current, and voltage margin violations. Our algorithm provides a significant saving in CPU time with accuracy comparable to SPICE in the calculation of steady-state voltages.