Abstract
An accurate and time efficient model of CMOS gate driven coupled-multiple interconnects is presented in this paper for crosstalk induced propagation delay and peak voltage measurements. The proposed model is developed using the finite difference time domain (FDTD) technique for coupled RLC interconnects, whereas the alpha power law model is used to represent the transistors in a CMOS driver. As verified by the HSPICE simulation results, the transient response of the proposed model demonstrates high accuracy. Over the random number of test cases, crosstalk induced peak voltage and propagation delay show average errors of 1.1% and 4.3%, respectively, with respect to HSPICE results.
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