Abstract
A metal-oxide-semiconductor structure with a stepped oxide under a common gate metallization is investigated. The G(V) and C(V) curves strongly deviate from those of wafers with uniform oxide thicknesses: Three sharp G(V) maxima and a well structured C(V) curve are seen. A general equivalent network has been established for the description of the behavior of the structure. By choosing special bias conditions, the network can be reduced to simpler configurations. In this case all the network elements are accessible from independent measurements (secondary electron microscopy, control samples), so that the C(V) curve can be reconstructed solely from geometrical and technological data for its essential portions. The network is exploited for a separate determination of the surface-state density underneath the thin and the thick oxide regions. This has been done for a series of thin/thick oxide combinations. A lateral field induced p-i junction is found underneath the thick/thin oxide boundary for appropriate biases, V. The G (ω;V=const.) and C(ω;V=const.) analysis delivers the (forward)conductance and capacitance of the junction.
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