ADC testing using digital stimuli

Abstract

The Analogue-to-Digital Converter (ADC) is one of the most typical and widely used mixed-signal circuits. They are applied in video, audio, high-speed communications systems and so on. Many ADCs are integrated into platform-based designs, the architecture which normally contains of standard blocks such as memories, digital processors, RF and analogue front-ends. As testing such a system is a complex task, the related test cost of the platforms is a major part of over all chip costs. The test cost of ADCs has a relatively high percentage of the total test cost of the chips. The major challenges of the ADC production test cost are the expensive test equipment and the long test times. An architecture of an ADC test infrastructure in a platform-based design has been proposed in our research, which consists of the embedded digital processor(s), the ADC under test, aiding digital test stimuli circuits and memory. The embedded processor can generate the test input signal with the aiding circuits and post-process the output data. The aiding circuits adapt the normal digital signal from the processors to be more suitable for ADC testing. The memory can store the conversion output data. In this thesis, we basically propose three novel methods. Based on our proposed test infrastructure, either signature results are used to only filter out the faulty devices or accurately predicted dynamic results of the ADCs can be obtained. Both the test input signal generation and post-processing can be carried out on the embedded processor. In this way, it relaxes the requirements of the ATE, which is normally the bottleneck in ADC production testing. It is especially suitable for a multi-site test environment. As result, it can reduce the test time and the cost of ADC production testing.