Adaptive Optimization Design of Vector Error Diffusion Algorithm and IP Core for FPGA

Abstract

A vector error diffusion algorithm can obtain better halftone results than a scalar error diffusion algorithm in digital printing, thus, extensive research work about the vector error diffusion has been done to decrease the time that users wait for printing. In this paper, an improved vector error diffusion IP core is proposed. The IP is implemented in FPGA and can meet the requirement of real-time printing by the improvements as follow: three R G B planes are computed in parallel, a matrix-valued error filter is designed to diffuse error among the three planes, matrix-valued pre-stored memory is created to speed multiplications and five stage pipelines are adopted to replace traditional sequential processes. Based on the improvements, we build a practical hardware test system on the SoCKit platform. The test results show that optimal algorithm only needs one clock circle to get the halftone result of a pixel on average and can meet the requirements of practical printing.