Adaptive body biasing technique based digital LDO regulator for transient response improvement

The increasing penetration of Distributed Generators (D.G.) into the existing power system has brought some real challenges regarding the transient response of electrical systems. The injection of D.G.s and abrupt load changes may cause massive power, current, and voltage overshoots/undershoots, which consequently affects the equilibrium of the existing power system and deteriorate the performance of the connected electrical appliances. A robust and intelligent control strategy is of utmost importance to cope with these issues and enhance the penetration level of D.G.s into the existing power system. This paper presents a Modified Particle Swarm Optimization (MPSO) algorithm-based intelligent controller for attaining a desired power-sharing ratio between the M.G. and the main grid with an optimal transient response in a grid-tied Microgrid (M.G.) system. The proposed MPSO algorithm includes an additional parameter named best neighbor particles (rbest) in the velocity updating equation to convey additional information to every individual particle about all its neighbor particles, consequently leading to the increased exploration capability of the algorithm. The MPSO algorithm optimizes P.I. parameters for transient and steady-state response improvement of the studied M.G. system. The main dynamic response evaluation parameters are the overshoot and settling time for active and reactive power during the D.G. connection and load change. Furthermore, the performance of the proposed controller is compared with the PI-PSO-based MG controller, which validates the effectiveness of the proposed M.G. control scheme in maintaining the required active and reactive power under different operating conditions with minimum possible overshoot and settling time.

The proposed wearable biomedical device as given in Fig. 1.12 includes analog and noise sensitive blocks that should be supplied by LDO regulator in order to support a clean and a low voltage ripple. LDO regulators are widely utilized in PMU as they provide fast response, small area, and full integration. However, with the increase of process variation and the reduction of the supply voltage, the analog amplifier becomes challenging to design. As such, many research focus moves towards digital LDO (DLDO) regulator design as it can operate at a low supply voltage level. Yet digital logic circuits introduce more delay which affects the transient response. This chapter discusses the state of the art DLDO regulators in the literature. Then, we propose a DLDO regulator based on a ratioed logic comparator circuit that totally eliminates the digital loop delay. After that we present the simulation results in 22 nm FDSOI technology.

This paper studies about a neural network control for digitally controlled method for PWM dc-dc converters. Especially, we focus on an overcompensation phenomenon which causes from a neural control term for the transient response improvement. It is known that a nonlinear prediction can improve the transient response, however, it also causes the overcompensation since the non-linear behavior mainly due the time delay of the converter system and digital control computation. In this study, an estimated current information from a steady state equation of the output voltage is used to suppress the overcompensation by the neural network control. The suppression method is simply realized by a mode change of the neural network control term in the transient state. From simulation results, it is confirmed that the proposed method can work both to improve the transient response and to suppress the overcompensation phenomena simultaneously.

This paper presents a fast and an efficient digital LDO (DLDO) regulator utilizing a clock-less ratioed logic comparator (RLC). In addition to eliminating the clock, the proposed RLC-DLDO removes the shift registers used in the conventional DLDO. It achieves a transient speed improvement in the ns range and a quiescent current reduction by 9X over the conventional DLDO design that targets μA load current. The RLC-DLDO consists of RLC, PMOS power switches and control unit. The RLC compares between the reference and the load voltage and generates a single bit that turns on/off the PMOS switches. Unlike the clocked comparator, the RLC is an event-driven design that continuously responds to the voltage difference. The control unit provides digital bits to control the power switches and the RLC circuit in order to support different output voltage levels. The RLC-DLDO has an input voltage range between 0.8V and 0.6V and generates an output voltage range between 0.7V to 0.5V for load current between 10μA and 500μA. The design is implemented in 22nm FDSOI and occupies an active area of 0.0171mm2. The simulation results show that the peak efficiency is 99.9% and the load transient response time is 5ns at V L =0.5V.

As an important unit of power management system, traditional analog low-dropout regulator (ALDO) is widely used in System-on-Chip (SoC) design to provide stable and pure power for each sub-circuit block. However, in ultra-low-power design applications, low quiescent current greatly affects the loop gain of ALDO. Digital low-dropout regulator (DLDO) has good low-voltage working ability, process scalability and diversified control schemes, which is more suitable for low-power SoC design. However, a large number of digital circuits with fast switching devices will produce large load current changes, so DLDO needs fast transient response speed to adjust load changes. In recent years, DLDO can be divided into synchronous DLDO and asynchronous DLDO according to different control methods. Among them, the design structure of synchronous DLDO is relatively simple. It depends on an independent global clock, and there is a tradeoff between speed, accuracy and power consumption. When the clock frequency increases, the system needs fast transient response, but the power consumption will increase proportionally, and the current efficiency and loop stability will decrease. Using large output capacitor to deal with load transient is not conducive to improve chip integration. Although asynchronous DLDO can improve the response speed based on the advantages of asynchronous control scheme, the stability of DLDO will face greater risks. Therefore, this paper will introduce several transient response enhancement technologies that do not sacrifice system power consumption, accuracy or stability. It includes adaptive frequency technology and fast response algorithm to improve the transient response speed of synchronous DLDO, event-driven solution and coarse and fine adjustment technology to improve the transient response speed of asynchronous DLDO. On this basis, a typical DLDO structure with excellent performance in the recent 10 years is given.

In this work, multiphase digital low-dropout (MP-DLDO) regulators are designed with resonant rotary clocks (ReRoCs) in order to improve on the tradeoff of conventional DLDOs between current efficiency and transient response speed. The proposed DLDOs are multiphased, coined MP-DLDOs, designed with a clock-gated control technique to provide high current efficiencies along with transient response improvements at GHz frequency levels. The multiple phases within the MP-DLDO are served with ReRoCs that provide: 1) a robust high-speed low-power resonant clock distribution solution for the synchronous elements in the multiphase DLDO architecture and 2) improve the transient response characteristics (dynamic voltage scaling (DVS) speed and voltage ripple) while saving power in the controller circuitry. The proposed MP-DLDOs are distributed across the chip to achieve low voltage ripple. SPICE simulations are performed on post-layout, parasitic-extracted models to evaluate the MP-DLDO architecture on open-source digital cores, with performance metrics that include the voltage ripple reduction, transient response speed improvement, and power savings in the control logic. The proposed MP-DLDO architecture, evaluated on an RISC-V design, demonstrates a DVS speed of 6.5 V/μs and an output voltage ripple of 21.1 mV (38% reduction when compared to a conventional DLDO) with a sampling frequency of 2 GHz.

A fast transient response to a step load change is very essential in a switch mode power supply. The transient response can be improved by means of feedback control method. There are two feedback control methods widely used for SMPS, they are voltage mode control (VMC) and peak current mode control (PCMC). A simulation study on these feedback control methods has been done using Matlab/Simulink. It is found that the PCMC helps the SMPS for a faster transient response compared to the VMC. However, there are a few disadvantages of the PCMC which make it not possible for further transient response improvement. Hence, in this paper a novel feedback control technique is presented and it is called voltage injection switching inductor (VISI). This feedback control method provides a better transient response compared to PCMC. Detailed explanations of the novel method and simulation results are presented in this paper. The simulation results show improvement in terms of fast transient response.

Converter transient response is mainly limited by filter LC delay time, controller delay time and propagation delay time. It is a tradeoff between efficiency and transient response in the design. In isolated DC/DC converter, the bandwidth of opto-coupler has an extra strong effect on the system bandwidth improvement. This paper presents current injection method, switching mode current injection circuit only engaged in transient periods operating in high frequency at the secondary side to improve the bandwidth for better dynamic response while the main topology can operate in lower frequency for good efficiency. Simple voltage control for fixed switching frequency and stable operation, instead of hysteretic control, is carried out for current injection circuit. Finally, experimental results are given to verify the theoretical analysis

Wind generator transient response analysis and improvement using BESS

In this paper, a soft-start method for improvement of the transient response during the initial startup of power converters in building applications is proposed. Most dc loads have sensitive electrical characteristics regarding the input voltage. In such systems, the power converter is operated after connecting with dc loads to minimize the overshoot of the control voltage that may occur during connection to the loads. But whenever the power converter is started, the parameters in the circuit can differ, since the power converter is connected with various load types at each startup. This is disadvantageous for PI controller design for power converters. In order to solve this problem, a novel voltage control method using sliding-mode control theory is proposed. The advantage of the proposed voltage controller is that it is able to minimize an overshoot of the control voltage at the startup of the converter in terms of the types of loads or the magnitude variation of loads because a sliding mode controller has the robust characteristic of a variation in the parameters and load. The characteristics of three types of voltage controllers were compared through simulations and experiments. Despite the variations of the system parameters, the proposed voltage controller has fast response in the steady-state and robustness characteristics in the transient state. In addition, the proposed controller fundamentally minimizes the overshoot of the control voltage. The proposed controller was applied to a three-phase ac/dc converter, and the controller performance was verified.

This study presents a fixed-frequency hysteretic buck converter designed and fabricated using 0.18-µm complementary metal–oxide–semiconductor process. With a phase-locked loop (PLL)-based adaptive window control, the proposed buck converter can achieve a fixed switching frequency, and this frequency can be tuned within a certain range through a reference clock frequency. Concurrently, a novel auxiliary circuit is proposed to monitor the converter's output loading dynamics to reduce the converter's transient recovery time. It will also help to regulate the output voltage at the steady-state operation as well. With the supply voltage ranging from 3 to 4.2 V and an output voltage of 1.8 V, the simulated switching frequency is maintained at 10 MHz because of the PLL control. The transient response time is only 0.3 and 0.4 µs for a 400 mA step-up load and step-down load, respectively.

To compare the effects of the sustained exposure to inhaled nitric oxide (NO) on pulmonary gas exchange, cardiovascular function and lung mechanics in newborn lambs with pulmonary hypertension induced by tracheal instillation of meconium. Fifteen newborn lambs (<6 d old) were studied in three groups (n = 5): control, and pulmonary hypertension (5 mL x kg[-1] of a 20% meconium solution) with or without inhaled NO (20 ppm) exposure. Heart rate, systemic and pulmonary arterial pressures, arterial pH and blood gases, cardiac output, and pulmonary mechanics were measured. The exposure to inhaled NO in lambs with pulmonary hypertension, induced by experimental meconium aspiration, produced a transient response. There were a transient improvement in gas exchange, a decrease in pulmonary arterial pressure and airway resistance, without changes in cardiovascular profile. The transient and incomplete response to inhaled NO in experimental MAS might be related to the fact that hypoxemia is not only due to pulmonary vasoconstriction but also to parenchymal lung disease. We hypothesize that this poor and transient response could probably be avoided if strategies that increase lung recruitment, were applied before inhaled NO exposure.

With the advent of on-chip digital low-dropout (DLDO) regulators, distributed on-chip voltage regulation has become increasingly promising. Environmental and operating conditions have been demonstrated to degrade DLDO performance, which directly affects execution accuracy. The area overhead (OH) needed to compensate aging-induced voltage noise degradation can be significant. Accordingly, in this paper, the algorithmic noise tolerance of certain processor components is exploited as an area–quality control knob to trade the program output quality for area OH. Furthermore, efficient and lightweight techniques utilizing a unidirectional shift register and reduced clock pulsewidth triggering are proposed to realize a novel aging-aware (AA) DLDO to achieve a better area and quality tradeoff. Owing to the large number and distributed nature of voltage regulators, with the proposed design, both the number of regulators utilized in the system and the size of each local regulator are scalable to satisfy the needs of different applications and processor components with varying algorithmic noise tolerance. It is demonstrated through simulation of an IBM POWER8 like processor that the proposed AA design can achieve up to, respectively, 43.2% and $3\times $ transient and steady-state performance improvement. Additionally, more than 10% area OH saving can be achieved over a 5-year period.

Digital low-dropout voltage regulators (DLDOs) have drawn increasing attention for the easy implementation within nanoscale devices. Despite their various benefits over analog LDOs, disadvantages may arise in the form of bias temperature instability (BTI) induced performance degradation. In this Chapter, conventional DLDO operation and BTI effects are explained. Reliability enhanced DLDO topologies with performance improvement for both steady-state and transient operations are discussed. DLDOs with adaptive gain scaling (AGS) technique, where the number of power transistors that are turned on/off per clock cycle changes dynamically according to load current conditions, have not been explored in view of reliability concerns. As the benefits of AGS technique can be promising regarding DLDO transient performance improvement, a simple and effective reliability aware AGS technique with a steady-state capture feature is proposed in this work. AGS senses the steady-state output of a DLDO and reduces the gain to the minimum value to obtain a stable output voltage. Moreover, a novel unidirectional barrel shifter is proposed to reduce the aging effect of the DLDO. This unidirectional barrel shifter evenly distributes the load among DLDO output stages to obtain a longer lifetime. The benefits of the proposed techniques are explored and highlighted through extensive simulations. The proposed techniques also have negligible power and area overhead. NBTI-aware design with AGS can reduce the transient response time by 59.5% as compared to aging unaware conventional DLDO and mitigate the aging effect by up to 33%.

This paper describes transient response improvement of digital PID and I-PD controlled synchronous rectification buck-type dc-dc converter using feedforward compensator. Numerical formulae of the feedforward compensator were introduced by taking into account the relational expression including input voltage, output voltage, load current and ON-time of high-side switch. The steady-state characteristics of the converter with feedforward compensator were the same as the converter without one. However, input and load transient response were significantly improved.