Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack

Abstract

We report a gate-first TiLaO/CeO2n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56nm and threshold voltage (Vt) of 0.31V. This small EOT MOSFET was achieved by employing high-κ CeO2 interfacial layer with high bond enthalpy (795kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16nm technology node.