Achievement of High Flatness of Large Diameter Silicon Wafer in Double-Sided Polishing (Optimization of Polishing Conditions Based on Kinematical Analysis)

Abstract

Silicon (Si) wafers are the most commonly used substrates for the production of semiconductor devices. The design rule is miniaturization, and the chip size is increasing to improve the degree of the device integration. As the substrate, Si wafer is then required to be manufactured with higher flatness and larger diameter in order to meet the above demand. The double-sided polishing process is widely adopted as the finishing stage of the wafer manufacturing, because wafers with good surface quality and flatness can be obtained economically. However, the polishing technology has a serious problem : it is very difficult to set the appropriate conditions for stably polishing the Si wafer and wearing pad to high flatness in manufacturing. In this study, the optimization of double-sided polishing conditions was proposed and developed for overcoming the problem. As a basis, the model of the distribution of material removal on the wafer and the distribution of wear on the pad was developed based on kinematical analysis. The amounts of removal and wear are considered to be proportional to the sliding distance between wafer and pads. The optimization of the polishing conditions was performed utilizing a quasi-Newton method. As a result, the polishing conditions are clarified by minimizing the deviation of material removal distribution on the wafer and wear distribution on the pads, that is, achieving high flat wafer and pads.