Abstract
In this paper, a novel scheme for the generation of pseudo-exhaustive two-pattern tests for combinational modules under test is presented. The proposed scheme utilizes an accumulator with 1's complement adder to generate the patterns in time equal to the theoretical minimum. Since accumulators are commonly found in current, high-speed signal processing VLSI circuits, the presented scheme may prove a practical solution for the pseudo-exhaustive testing of such circuits for delay and stuck-open faults. Comparisons of the proposed scheme with previously proposed schemes for pseudo-exhaustive two-pattern testing reveals that the proposed generator compares favorably with respect to the required hardware overhead.
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