Abstract
Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.
Highlights
Scaling and Moore’s law, that sets the footprint area of a transistor to scale by a factor 2, that is the transistor gate length L to scale by a factor √2, every 2 years, have been the driving force of the electronic industry[1]
The source- and drain- (S&D) extension regions are doped with a concentration NSD
Ohmic contacts are assumed with S&D bias VS = 0 V and VD, respectively
Summary
Scaling and Moore’s law, that sets the footprint area of a transistor to scale by a factor 2, that is the transistor gate length L to scale by a factor √2, every 2 years, have been the driving force of the electronic industry[1]. As a rule of thumb, in a multi-gate device, the channel thickness ts has to be of the order of 1⁄2 L in order to keep the electrostatic integrity leading to ts of a few nm only in modern advanced nanoscale technologies[7] At such value of ts, conventional 3D semiconductors, like Si, or possible high-mobility channel-replacement materials like Ge3 or III–V5, suffer from quantum-confinement effects that strongly deteriorate their performance (e.g., current drive, gate coupling, mobilities...)[8,9,10], as well as, lead to increased variability (e.g., strong thresholdvoltage variations with surface roughness for instance)[2,10,11]. The D2-FET concept further addresses the difficult challenge of doping in nanoscale devices (https://irds.ieee.org/editions/2018) and 2D materials in particular[19], and the need for chemical doping could be suppressed
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