A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS

Abstract

Excessive timing margins are usually added in the wide-voltage-range design due to process, voltage and temperature (PVT) variations, which can be eliminated by adaptive voltage scaling (AVS). Some traditional Razor-based designs replace endpoint flip-flops with latches and ensure data sampled correctly. The duration of time-borrowing and the short path problem make the minimum-delay constraint worthy of consideration. To overcome the minimum-delay problem in the latch-based error detection and correction (EDAC) techniques, we propose a solution using a pulsed-latch and transition detector (TD). This method utilizes time-borrowing characteristics of the latch to ensure the correct function. To detect timing violations and minimize area overhead, we design a 15-transistor transition detector which is able to operate at a wide voltage range, from near-threshold voltage (NTV) to super-threshold voltage (STV). To minimize the overhead of pulse generators, a physical allocation-aware pulse generator insertion algorithm is presented to identify each desired group of a pulse generator and a pulsed-latch group. The proposed scheme is implemented in an 8-bit AES circuit through an automatic insertion flow and fabricated in a 28nm CMOS process. Chip measurements demonstrate that the whole design achieves up to 64.3% energy saving as compared to the conventional worst-case design at a small price of 4.3% area overhead.