Abstract
In this paper, a high resolution and wideband incremental ADC with extended counting is described and analyzed. The modulator introduced inter-stage gain to reduce the quantization noise without adding any hardware. Also, a gain scaling technique was used to decrease the power consumption by reducing the integrators' output swing. First, the 2nd order incremental ΔΣ ADC and 11-bit SAR ADC were measured separately. Second, the incremental ΔΣ ADC with extended counting was tested. It achieved a 91.6 dB dynamic range and 77.8 dB SNDR in the 0---1.25 MHz signal band. The total power consumption is 53.5 mW with dual power supplies (analog 3.3 V, digital 1.8 V).
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