A VLSI design for energy extraction and pileup prevention for high count-rate scintillation signals

Abstract

A very large scale integration (VLSI) all digital processor is proposed to recover photon energy deposited in a Nal scintillation detector on Compton based single photon emission computed tomography (C-SPECT) system for high count-rate events where multiple gamma-rays are overlapped in time. Compared with digital-analog hybrid implementation, this all digital solution offers more flexibility in accommodating different scintillators and higher noise immunity. The digital architecture consists of a three-value median filter, new event start-point arbitrator, high resolution timer, first in first out (FIFO) external interface module, and event energy extractor, which can be realized with traditional application-specific integrated circuit (ASIC) procedures or on modern field programmable gate arrays (FPGA). In the event energy extractor, a pipelined look-up-table calculation unit is designed to compute the exponential multiplication, which not only increases working frequency to 400 MHz but also avoids floating point multiplication. After filtering the 10-bit digital scintillation signals from an external analog to digital (A/D) converter at the rate of 100 Msps, the kernel circuits recover the energy deposition of gamma rays by subtracting the remnant overlapped energy from the preceding sums integrated from the event starting point. Then, the extracted event energy and its corresponding trigger timing are pushed into the output FIFO buffer. The chip for NaI scintillation detector is implemented by using the TSMC 0.18 /spl mu/m standard cell with an estimated die area of 1.0/spl times/1.0 mm/sup 2/ and a 1.8 V power supply on the CAD system. Experiment results show-that the designed all digital PPE chip is able to recover the photon energy correctly not only at low count rates but also at count rates as high as 100 kcps with energy resolutions about 10-15% FWHM for different count rates.