Abstract
This paper presents a threshold detection circuit with an adjustable detection window designed in IBM 90nm CMOS technology. Together with a RF multiplier, it realizes the back-end section of a transmitted reference ultra wideband receiver, which is yet to be reported in literature. The comparator section uses an operational trans-conductance amplifier core and avoids the use of sample and hold and control voltage generator circuits which reduces the electronic overhead needed for the architecture. The design is tested at a bit rate of 0.1~2.0 Gbps and the decision circuit consumes 9.14 mW power from a 1.2 V bias supply with a maximum speed to power ratio of 218.8GHz/W. When compared against other reported comparators, the detection circuit shows improved performance in terms of speed and power dissipation.
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