A subthermionic tunnel field-effect transistor with an atomically thin channel

The continuous MOSFET device scaling turned short channel effects and leakage currents into major issues, in a way that new technologies should be considered for further technology nodes. In this context, Tunnel Field Effect transistors (TFETs) are a promising alternative, in which gate controlled band-to-band tunneling (BTBT) replaces drift-diffusion in providing carrier injection[1-2]. The built-in tunnel barrier makes it possible to reach subthreshold swing (SS) values lower than ln(10).k.T/q (60mV/dec at room temperature), reducing power dissipation and leakage currents[1-2]. However low on-state current and ambipolarity are relevant issues, some simple circuits can be used to infer how recent devices compare to traditional structures. In this work, TFET devices have been studied based on experiments and simulations of a basic current mirror. Their performance has been compared to FinFETs for temperatures ranging from 300K to 500K. Fig.1 represents schematically the basic current mirror, with a fixed bias in the input transistor and a varying drain voltage applied to the output device. All measurements and simulations have been performed with VS1=VS2=1.7V and with VDS2ranging from -0.5V to 1.0V. Input and output drain currents have been analyzed. First of all, this circuit has been experimentally studied, making use of TFETs (Fig.2) and FinFETs (Fig.3) with different values of channel length (1µm and 10µm) and width (1µm and 0.25µm). Since for TFET the input transistor is under a fixed bias, its drain current is basically constant. Meanwhile, the output drain current decreases when VD2gets closer to 1.0V, since it is not in the “saturation-like” region anymore. Comparing Figures 2 and 3, it is clear that TFETs and FinFETs, respectively, present the same susceptibility to the channel width variation. On the other hand, it is quite interesting to notice the difference in terms of channel length dependence. Comparing IDSwhen L gets 10 times larger, FinFETs present the expected 10 times decrease, while TFETs reveal a reduction of no more than 20%, since TFET is not as length dependent as FinFET. Based on these observations, simulations have been performed to reveal the channel length influence on the suitability of both TFETs and FinFETs for current mirror circuits. All the simulations have been performed for an input transistor with L1 = 60nm, while the output transistor had L2 ranging from 20nm to 100nm. Figure 4 shows the IDS2/IDS1 ratio for each case when VDS2=0V, with the perfect matching situation represented by L2=L1=60nm. The results show that TFET is much less dependent on L2 than FinFET. Therefore, it is interesting to notice that the circuit presents a very good mirror behavior even when the transistors channel lengths do not exactly match. This is a consequence of the previously mentioned TFET working principle, with the tunneling happening quite close to the source/channel junction. The drain current is affected by L2only when it gets lower than 40nm, which may be explained by the impact of DIBT (drain induced barrier thinning) on TFETs[3]. On the other hand, a circuit with FinFETs loses its ability to mirror the input current when L2 changes. For instance, when L2 changes from 40nm to 100nm, the output drain current variation reaches 50%, while it varies less than 10% for TFETs. In the worst-case scenario for both of them (L2=20nm), the output drain current deviation from the perfect matching situation reaches 80% for TFETs and 230% for FinFETs. Finally, Fig.5 illustrates the temperature impact on the current mirror output current, revealing 2 main differences between TFETs and FinFETs. The first one is the opposite trend, with an ascending curve only for the TFET case. This may be explained by the differences in the transport mechanisms for each case. In TFET devices, higher temperatures increase band-to-band tunneling, which is the most important component for high values of VDS. Meanwhile, the mobility in FinFETs is degraded, resulting in a drain current decrease to almost half of its original value. Besides, dashed lines in Fig.5 reveal the susceptibility to the output drain voltage. These curves show the obtained results for VD2=-0.5V and VD2=+0.5V. While for TFETs this variation causes an output current deviation of 6%, for FinFETs the deviation reaches almost 30%. In other words, circuits with TFETs tend to present a larger compliance voltage, which is exactly the maximum voltage variation that still results in an acceptable output current. Therefore, TFETs present a better suitability in terms of mirroring the input current even for output bias variations. [1] W.M.Reddick et al.,Appl.Phys.Lett.,67,494-496,(1995). [2] T.Krishnamohan et al.,Tech.Dig. IEDM 2008,947-950,(2008). [3] M.D.V.Martino et al.,SBMicro 2014,1,1-4,(2014). Figure 1

Thickness or the number of layers in 2D semiconductors is a key parameter to determine the material's electronic properties and the overall device performance of 2D material electronics. Here, we discuss the engineering practice of optimizing material and device parameters of phosphorene field-effect transistors (FETs) by means of self-consistent atomistic quantum transport simulations, where the impacts of different numbers of phosphorene layers on various device characteristics are explored in particular, considering two specific target applications of high-performance and low-power devices. Our results suggest that, for high-performance applications, monolayer phosphorene should be utilized in a conventional FET structure since it can provide the equally large on current as other multilayer phosphorenes (Ion > 1 mA/μm) without showing a penalty of relatively lower density of states, along with favorableness for steep switching and large immunity to gate-induced drain leakage. On the other hand, more comprehensive approach is required for low-power applications, where operating voltage, doping concentration, and channel length should be carefully engineered along with the thickness of phosphorene in tunnel FET (TFET) structure to achieve ultra-low leakage current without sacrificing on current significantly. Our extensive simulation results revealed that either bilayer or trilayer phosphorene can provide the best performance in TFET with the maximum Ion/Ioff of ∼2 × 1011 and the subthreshold swing as low as 13 mV/dec. In addition, our comparative study of phosphorene-based conventional FET and TFET clearly shows the feasibility and the limitation of each device for different target applications, providing irreplaceable insights into the design strategy of phosphorene FETs that can be also extended to other similar layered material electronic devices.

Reductions in transistor size have improved functionality of transistors and lowered costs of electronic processors. However, as transistors decrease in size, quantum tunneling causes increased leakage currents and power consumption. To resolve power consumption issues, tunnel field-effect transistors (TFETs) utilizing band-to-band tunneling (BTBT) have been suggested. Such devices can overcome the 60 mV/dec subthreshold swing (SS) limit that is a disadvantage of conventional metal-oxide-semiconductor field-effect transistors (MOSFETs), but only a limited number of TFETs have achieved this at 300 K. Here, we report complementary trilayer–bulk black phosphorus (BP) heterojunction TFETs with an SSmin of 17.7 mV/dec (21.3 mV/dec) for p-type (n-type) operation. In the same devices, SS ≫ 60 mV/dec is exhibited when BTBT occurs within the trilayer BP, indicating that BTBT between the heterojunction of a trilayer–bulk BP is the key to achieving a subthermionic SS. Our work demonstrates the utility of BP heterojunctions in developing energy-efficient switches.

As Moors law is concerned, down scaling of conventional CMOS technology results in, rapidly approaching fundamental limits. Alternative device structures are constantly proposed to substitute the traditional CMOS type devices. That type of device is a gated reverse-biased structure, commonly referred to as Tunnel Field-Effect Transistor (TFET). This device is particularly suitable for ultra-low-power applications. The most prominent feature of TFETs is their capacity for producing an inverse sub-threshold swing (SS) smaller than the 60 mV/decade thermal limit (at 300 K) of conventional inversion mode MOSFETs. Sub-thermal SS is achievable because, the drain current in TFETs is produced by carrier injection from source to channel which is predominantly governed by quantum mechanical band-to-band tunnelling (BTBT), rather than by diffusion as in MOSFETs. In, this paper we will show the silvaco TCAD simulation results for both conventional MOSFET and Tunnel field effect transistor. From the results, it is evident that TFET is suitable for ultra-low power applications.

With the transistor dimensions scaling down to a few atoms, quantum phenomena - like quantum tunneling and entanglement - will dictate the operation and performance of the next generation of electronic devices, post-CMOS era. While quantum tunneling limits the scaling of the conventional transistor, Tunneling Field Effect Transistor (TFET) employs band-to-band tunneling for the device operation. This mechanism can reduce the sub-threshold swing (S.S.) beyond the Boltzmann's limit, which is fundamentally limited to 60 mV/dec in a conventional Si-based metal-oxide-semiconductor field-effect transistor (MOSFET). A smaller S.S. ensures TFET operation at a lower supply voltage and, therefore, at lesser power compared to the conventional Si-based MOSFET.However, the low transmission probability of the band-to-band tunneling mechanism limits the ON-current of a TFET. This can be improved by reducing the body thickness of the devices i.e., using 2-Dimensional (2D) materials or by utilizing heterojunction designs. In this thesis, two promising methods are proposed to increase the ON-current; one for the 2D material TFETs, and another for the III-V heterojunction TFETs.Maximizing the ON-current in a 2D material TFET by determining an optimum channel thickness, using compact models, is presented. A compact model is derived from rigorous atomistic quantum transport simulations. A new doping profile is proposed for the III-V triple heterojunction TFET to achieve a high ON-current. The optimized ON-current is 325 uA/um at a supply voltage of 0.3 V. The device design is optimized by atomistic quantum transport simulations for a body thickness of 12 nm, which is experimentally feasible. However, increasing the device's body thickness increases the atomistic quantum transport simulation time. The simulation of a device with a body thickness of over 12 nm is computationally intensive. Therefore, approximate methods like the mode-space approach are employed to reduce the simulation time. In this thesis, the development of the mode-space approximation in modeling the triple heterojunction TFET is also documented.In addition to the TFETs, quantum computing is an emerging field that utilizes quantum phenomena to facilitate information processing. An extra chapter is devoted to the electronic structure calculations of the Si:P delta-doped layer, using the empirical tight-binding method. The calculations agree with angle-resolved photoemission spectroscopy (ARPES) measurements. The Si:P delta-doped layer is extensively used as contacts in the Phosphorus donor-based quantum computing systems. Understanding its electronic structure paves the way towards the scaling of Phosphorus donor-based quantum computing devices in the future.

The rapid development of mobile and internet‐of‐thing devices demands continuous scaling of metal–insulator–semiconductor field‐effect transistors for high‐resolution and low‐power displays. However, such technology is limited by inadequate scaling of supply voltage and sophisticated dielectric engineering. Here, to enable continued scaling, indium–gallium–zinc‐oxide (InGaZnO) tunnel field‐effect transistor (TFET) and junction field‐effect transistor (JFET) are designed and fabricated based on vertically stacked black phosphorus (BP)/InGaZnO van der Waals heterojunctions. By varying BP thickness, BP/InGaZnO heterojunctions can be operated as forward rectifying diode, Zener diode, and backward rectifying diode, respectively. Room‐temperature negative‐differential‐resistance behavior with large peak‐to‐valley ratio of 2.1 and high tunneling current density of 160 mA mm−2 is obtained in thick‐BP/InGaZnO heterojunction. On this basis, sub‐thermionic subthreshold swing (SS) of 11 mV dec−1 is achieved in InGaZnO TFET. Meanwhile, the InGaZnO JFET based on thin‐BP/InGaZnO heterostructure exhibits good transistor performance of on/off ratio exceeding 105, high field‐effect mobility of 23.5 cm2 V s−1, negligible hysteresis, and improved SS of 83 mV dec−1. The BP/InGaZnO heterojunction is possibly the only device architecture so far to realize the amorphous metal‐oxide‐semiconductors TFET and JFET, thus providing promising pathways for further thin‐film transistor technology.

As a potential candidate for solid-state switches in low-power electronic circuits, the Tunnel Field Effect Transistor (TFET) has attracted the attention of device designers in the past few years. Although simulations have shown that ideal hetero TFETs can achieve sub-thermal sub-threshold swing (SS), the fabrication of a TFET with sufficient on-current and sub-thermal SS over a few decades of drain current remains to be done. Non-idealities in a TFET such as interface traps, band tails, or surface roughness exhibit stronger influence on TFET characteristics in the sub-threshold region. In Ref. [1] we observed that among all of these non-idealities the strongest effect is due to interface traps. On the other hand, simulations have shown that channel quantization severely degrades the on-current [2]. In this work, we analyse experimental transfer characteristics of InAs/Si nanowire TFETs (diameter « 100 nm) and find reasons for the degradation of SS and on-current. We give an estimate for the D it that still would allow a sub-thermal SS.

Tunneling field effect transistors (TFETs) based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low power devices. Here, we investigate the TFETs based on two different integration types: in-plane and vertical heterostructures composed of two kinds of layered phosphorous (β-P and δ-P) by ab initio quantum transport simulations. NDR effects have been observed in both in-plane and vertical heterostructures, and the effects become significant with the highest peak-to-valley ratio (PVR) when the intrinsic region length is near zero. Compared with the in-plane TFET based on β-P and δ-P, better performance with a higher on/off current ratio of ~ 106 and a steeper subthreshold swing (SS) of ~ 23 mV/dec is achieved in the vertical TFET. Such differences in the NDR effects, on/off current ratio and SS are attributed to the distinct interaction nature of the β-P and δ-P layers in the in-plane and vertical heterostructures.

In this paper, we investigate the channel length (L CH ) of the silicon-on-insulator (SOI) n-type tunneling field effect transistor (NTFET) with the respect of device performance. 2D-device simulation was used for simulating the devices with 30 nm gate length of SOI NTFET with 10 nm thin buried oxide (t BOX ) and 7 nm thin silicon body (t si ). The device performance, such as threshold voltage (V TH ), ON current (I ON ), OFF current (I OFF ), and subthreshold swing (SS) was extracted from the current-voltage characterizations of SOI NTFET. The longer the channel length, the lower the SS value and I ON /I OFF ratio obtained in these simulations. Unfortunately, the SS values obtained throughout these simulations were still higher than the typical SS value of TFET device which is supposed to be lower than 60 mV/decade. However, the SS values obtained was still lower compared to the SS value of the MOSFET. On the other hand, I ON /I OFF ratio still high which is better for switching operation of the devices.

From inception, the advent of electronics industry has been propelled by advancements made in the field of integrated circuit (IC) technology. In recent years, continuous miniaturization along with batch fabrication of ICs has resulted in high performance to cost index of modern electronics system. This tremendous growth in the semiconductor IC industry has been due to the expansion in the material set, novel device design, and innovations in circuit and architectural levels. Silicon (Si)-based metal oxide semiconductor field-effect transistor (MOSFET) has been the cornerstone device for the growth of IC industry, especially for commercial electronics application. Over the years, continuous scaling of Si MOSFET has resulted in the improvement in performance to cost index. However, in the sub-nano meter technology regime, the performance of MOSFET devices has been limited due to short-channel effects (SCEs) like subthreshold conduction, drain-induced barrier lowering (DIBL), high leakage current, to mention a few. Even though innovative MOSFET designs based on gate and channel engineering like double gate (DG) MOSFET, dual material gate (DMG) MOSFET, dual material surrounding gate (DMSG), etc. structures have been reported, a major performance limitation of such devices has been the limit of scale supply voltage due to the subthreshold swing of value 60mV/decade at room temperature. A solution to continue scaling and improve the performance of ICs is an alternative device, that is, tunnel field-effect transistor (TFET). Compared to a conventional MOSFET device, a TFET has advantages in terms of high ON current (ION) to OFF current (IOFF) ratio, faster switching times, improved subthreshold swing (SS), thereby low leakage current and low power consumption. The aforementioned characteristics of TFET devices provide them an edge over conventional MOSFET for high-speed and low power applications. In addition, in recent years, in the field of healthcare, TFET-based biosensors have been extensively explored as an alternative to micro/nano electro-mechanical systems (MEMS/NEMS)-based chemical/biological sensors. Compared to MEMS/NEMS sensors, TFET-based sensors hold advantages like better integration with CMOS process flow, simplicity of fabrication, relatively mechanical stability, to mention a few. This treatise encompasses examples of TFET devices with various configurations of TFET devices for numerous applications. In this chapter, we elucidate silicon (Si), germanium (Ge), and silicon-germanium (SiGe) materials-based TFET devices. The focus of this chapter is to explain the basic device operation of TFET with mathematical models. Further, a comparison of various TFET devices considering their geometry and material selection is performed. In the later sections, various device configurations and operations of Si TFET, Ge TFET, and SiGe TFET are analyzed, followed by the design challenges and future.

The low on-current and direct source-to-drain tunneling (DSDT) issues are the main drawbacks in the ultrascaled tunneling field-effect transistors based on carbon nanotube and ribbons. In this article, the performance of nanoscale junctionless carbon nanotube tunneling field-effect transistors (JL CNTTFETs) is greatly improved by using the synergy of electrostatic and chemical doping engineering. The computational investigation is conducted via a quantum simulation approach, which solves self-consistently the Poisson equation and the non-equilibrium Green’s function (NEGF) formalism in the ballistic limit. The proposed high-performance JL CNTTFET is endowed with a particular doping approach in the aim of shrinking the band-to-band tunneling (BTBT) window and dilating the direct source-to-drain tunneling window, while keeping the junctionless paradigm. The obtained improvements include the on-current, off-current, ambipolar behavior, leakage current, I60 metric, subthreshold swing, current ratio, intrinsic delay, and power-delay product. The scaling capability of the proposed design was also assessed, where greatly improved switching performance and sub-thermionic subthreshold swing were recorded by using JL CNTTFET with 5 nm gate length. Moreover, a ferroelectric-based gating approach was employed for more enhancements, where further improvements in terms of switching performance were recorded. The obtained results and the conducted quantum transport analyses indicate that the proposed improvement approach can be followed to improve similar cutting-edge ultrascaled junctionless tunnel field-effect transistors based on emerging atomically thin nanomaterials.

Enhancing TFET performance through gate length optimization and doping control in phosphorene nanoribbons

Since the continuous scaling down of the transistor channel length, extraordinary improvement is achieved in the switching speed. However, the rising leakage current degrades the power consumption seriously. In this regard, reducing supply voltage might be the most effective method. This requirement can be fulfilled well by tunnel field‐effect transistors (TFETs), because carriers transport via a band‐to‐band tunneling manner in the TFETs. Relying on the special transport mechanism, the TFETs often require band structure modulations and steep interfaces without trap state, which are challenging for bulk materials. Therefore, these challenges have boosted TFET designs based on low‐dimensional materials ranging from Si/Ge nanowires to state‐of‐art van der Waals heterostructures. Here, the key concepts of the currently developed TFETs are studied from the aspects of structure, material, transportation characteristic, and mechanism. According to the heterojunction bonding types, they can be divided into lateral and vertical TFETs in general. Furthermore, other related transistors based on tunneling are also included. Emerging problems and promotion methods toward these TFETs are introduced with the assistance of simulations. The main goal is to introduce the frontiers of TFET explorations and provide readers with a perspective on how to realize TFET applications in the future.

In this research work, a n-type silicon tunneling field effect transistor (TFET) has been designed and investigation has been carried out on its performances by altering different device parameters such as gate insulator dielectric constant, channel thickness, gate geometry, and channel length. The performances have been evaluated based on subthreshold swing, threshold voltage and Ion/Ioff ratio of the devices. The goal is to find a device which would simultaneously have a low subthreshold swing (SS), low threshold voltage, and a high Ion/Ioff ratio. It has been observed that having a double gate, short channel length, high-k dielectric, and low channel thickness leads us towards a compact design and the device exhibits very promising values of the aforementioned performance criteria. The most attractive proposition about a TFET is its ability to have a subthreshold swing lower than 60 mV/dec which is the theoretical limit of a MOSFET. In this study, an optimized device is obtained which has a subthreshold swing (point) of around 26 mV/dec and an Ion/Ioff ratio in the order of 1013. In addition, an inverter has been designed using a n-type TFET and a resistor to show the potential of TFETs to be used in logic circuits.

The adoption of three-dimensional (3D) integration has revolutionized NAND flash memory technology, and a similar transformative potential exists for logic circuits, by stacking transistors into the third dimension. This pivotal shift towards 3D integration of logic arrives on the heels of substantial improvements in silicon device structures and their subsequent scaling in size and performance. Yet, advanced scaling requires ultrathin semiconducting channels, which are difficult to achieve using silicon. In this context, field-effect transistors based on two-dimensional (2D) semiconductors have drawn notable attention owing to their atomically thin nature and impressive performance milestones. In addition, 2D materials offer a broader spectrum of functionalities -such as optical, chemical and biological sensing -that extends their utility beyond simple 'more Moore' dimensional scaling and enables the development of 'more than Moore' technologies. Thus, 3D integration of 2D electronics could bring us unanticipated discoveries, leading to sustainable and energy-efficient computing systems. In this Review, we explore the progress, challenges and future features that can be reliably manufactured, as was in the case of planar transistors, but to denote a new generation of process technology and devices that offer better performance and efficiency than their predecessors. This technique, known as monolithic 3D integration, involves the fabrication of thinner functional tiers separated by interlayer dielectrics and interconnected via monolithic inter-tier vias 12 . Several predictions and analyses already highlight the opportunities and advantages of monolithic 3D integration, including increased interconnect density, reduced electrical parasitic capacitance, enhanced energy efficiency and better performance [13] [14] [15] [16] . The future technologies will integrate novel 3D IC packaging and integration solutions with monolithically 3D-integrated individual chips. It is interesting to note that, despite its conception in the 1980s [17] [18] [19] , initial research on 3D integration was not actively pursued. This lack of interest was due to the then-prevalent trend of downsizing individual silicon-based transistor dimensions -a process made feasible through advances in materials science, electronics and nanofabrication. Consequently, transistor device dimensions shrank dramatically, transitioning from the micrometre regime to the realm of tens of nanometres. This period marked the introduction of high-κ dielectrics and strained silicon technology, as well as a shift from the classical planar field-effect transistor (FET) structure to newly emerging architectures. These include non-planar fin-shaped FETs (finFETs), gate-all-around (GAA) FETs (also known as nanosheet FETs, ribbon FETs, and multi-bridge channel FETs), and the potentially forthcoming forksheet FETs and complementary-FETs 20-22 . This evolution, which began in 1959, is depicted in Fig. 1a . However, it is challenging to scale transistors down further by reducing the thicknesses of semiconductor channels to less than 3 nm, because of inherent issues in silicon and other bulk semiconductors, such as increased charge carrier scattering at the semiconductorinsulator interface and subsequent mobility degradation 23, 24 . Along these lines, among other contenders such as carbon nanotubes and nanowires, ultrathin 2D semiconductors emerge as promising materials to facilitate the continued miniaturization of transistor dimensions 25 . From a materials perspective, 2D semiconductors, particularly transition-metal dichalcogenides (TMDs), have drawn tremendous attention in the past decade with demonstrations of high-quality waferscale synthesis, high-performance FETs, in-sensor and in-memory computing, optical, biological and chemical sensors, scaled FETs, and so on [26] [27] [28] . The progression in the development of growth technologies [29] [30] [31] [32] [33] [34] for 2D TMDs and the performance of their electronic devices [35] [36] [37] [38] [39] [40] [41] [42] [43] is illustrated in Fig. 1b . Apart from that, 2D materials also have applications in twistronics, spintronics, straintronics, valleytronics and flexible electronics [44] [45] [46] [47] [48] . Hence, as shown in Fig. 2 , 3D integration with 2D electronics not only presents alternative pathways for scaling individual devices in line with the 'more Moore' approach (continued scaling in accordance with Moore's law) but also provides diverse functionalities that can be leveraged to co-design and incorporate non-computational devices within the same platform, facilitating the realization of 'more than Moore' technologies 49 . In addition, theoretical studies have predicted that incorporating 2D electronics into monolithically integrated 3D chips can increase the integration density 50 . Here, we review the progress towards 3D integration of 2D electronics and its prospects and challenges. The review begins with a section on progress and challenges towards very-large-scale integration (VLSI) of 2D electronics followed by a summary of various 3D IC demonstrations that use 2D materials. Finally, we conclude this Review with a section on comprehensive device design considerations and the associated challenges. • 2D electronics must overcome several challenges before they can be adopted in commercial semiconductor chips. Some of the major challenges are discussed in the section 'Towards very-large-scale integration of 2D electronics'. • Research efforts in 2D material synthesis and device integration strategies must happen synergistically, with the goal of 3D integration, because silicon technology is already mature, with the most advanced nodes reaching the limits of planar integration in gate-all-around field-effect transistors. • 3D integration with 2D electronics not only demands the maturity of 2D electronics in the planar dimension but also poses new difficulties in the vertical direction. These difficulties must be thoroughly understood and addressed before 2D materials can be introduced into commercial electronics. • 2D materials have the potential to enable multifunctional chips by combining logic with memory and sensing in a 3D-integrated chip. Multifunctional chips containing 2D electronics should be developed with the goal of manufacturing task-specific semiconductor chips and thereby addressing various integration challenges. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.