A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS

Abstract

This paper reports a reference-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring fast and robust frequency acquisition without identifying the frequency error polarity. The key idea is a deliberately-current-mismatch charge-pump pair, which avoids the need of a complex high-speed data path or clock path during frequency acquisition. Prototyped in 28nm CMOS, our BBCDR covers a 47.6-to-58.8Gb/s PAM-4 input automatically. The achieved energy efficiency (≤0.25pJ/bit) and acquisition speed <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$[9.8(\text{Gb}/\mathrm{s})/\mu\mathrm{s}]$</tex> compare favorably with the prior art. Keywords—CMOS, reference less, single loop, half-rate, bang-bang clock and data recovery (BBCDR), frequency detector (FD), charge pump (CP), 4-level pulse amplitude modulation (PAM-4), zero (ZNC), positive (PNC), and negative (NNC) net current.