Abstract
The CMOS inverter plays an important role in digital CMOS design. Digital CMOS components in general depend on optimization techniques that have been proposed taking as reference the CMOS inverter. CMOS inverter optimization is often based on the equilibrium of the propagation times. The factors that affect these propagation times are numerous, namely: transistor dimensions, loading conditions, Miller effect and second order effects potentiated by the scaling of the CMOS technology. This paper explores new perspectives on the matching of the CMOS inverter propagation times, due to nonlinear loading conditions. Theoretical and simulation evidence shows that, the propagation times depend on several loading parameters when the load is a similar inverter rather than a simple linear capacitor.
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