A study of imprint-specific defects in the step and flash imprint lithography process

Abstract

Researchers have demonstrated that imprint lithography techniques have remarkable replication resolution and can pattern sub-5nm structures. However, a fully capable lithography approach needs to address several challenges in order to be useful in manufacturing. For successful manufacturing insertion of Step and Flash Imprint Lithography (S-FILTM) into a broad set of applications such as photonics, magnetic storage, and integrated circuits (ICs), the following practical process related challenges need to be addressed: (i) Printing sub-50nm structures with non-uniform pattern densities: (ii) Precise alignment and overlay with the ability to mix-and-match with photolithography; (iii) Availability of 1X templates; (iv) Achieving appropriate throughput for acceptable cost of ownership; and (v) Minimizing template and imprint process-induced defects to allow acceptable process yields. The last challenge - the ability to achieve low defect densities - is desirable for all applications. However, it is one of the biggest challenges for S-FIL to be accepted in IC fabrication. This article specifically focuses on this last challenge and presents the current status of defect reduction in S-FIL technology. The article starts out by providing a brief background of S-FIL technology, and by including a discussion of the overall status of S-FIL technology in Section 1. Next, an overview of the experiments performed including the defect inspection approaches used is provided in Section 2. Section 3 introduces the classes of defects that are relevant to the S-FIL process. It also provides recent defect data for each of these classes. Section 4 presents defect data gathered over the last three years and provides defect reduction trends over this period. Section 5 discusses the topic of template lifetime. Finally Section 6 provides some concluding remarks. The defect data presented here is based on a large number of short-loop experiments based on optical inspection of templates and wafers; these data are complemented by a modest number of high resolution e-beam inspections to provide insight into S-FIL specific defects at leading edge line widths.