A structured testability approach for multi-chip modules based on BIST and boundary-scan

Abstract

Products motivated by performance-driven and/or density-driven goals have started to use multi-chip module (MCM) technology, even though this technology still has several challenging problems, that need to be resolved before it becomes a widely adopted solution. Among the most challenging problems are achieving acceptable MCM assembly yields and meeting product quality requirements. Both of these problems can be significantly reduced by adopting adequate testing. Approaches which guarantee the quality of incoming bare (unpackaged) dies prior to module assembly, ensure the structural integrity and performance of the assembled MCMs, and help isolating defective parts prior to the repair process. This paper presents a structured testability approach that helps resolve the above problems. The approach can be adopted during MCM design and utilized during the manufacturing process. It is based on adopting Built-In-Self-Test (BIST) and boundary-scan and is in general independent of silicon, substrate or attachment technologies, hence it can be considered a generic solution.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>