A solid state streak camera

Abstract

A monolithic solid-state streak camera has been designed and fabricated in a standard 0.35 μm, 3.3V, thin-oxide digital CMOS process. It consists of a 1-D linear array of 150 integrated photodiodes, followed by fast analog buffers and on-chip, 150-deep analog frame storage. Each pixel's front-end consists of an n-diffusion / p-well photodiode, with fast complementary reset transistors, and a source-follower buffer. Each buffer drives a line of 150 sample circuits per pixel, with each sample circuit consisting of an n-channel sample switch, a 0.1 pF double-polysilicon sample capacitor, a reset switch to definitively clear the capacitor, and a multiplexed source-follower readout buffer. Fast on-chip sample clock generation was designed using a self-timed break-before-make operation that insures the maximum time for sample settling. The electrical analog bandwidth of each channels buffer and sampling circuits was designed to exceed 1 GHz. Sampling speeds of 400 M-frames/s have been achieved using electrical input signals. Operation with optical input signals has been demonstrated at 100 MHz sample rates. Sample output multiplexing allows the readout of all 22,500 samples (150 pixels times 150 samples per pixel) in about 3 ms. The chip’s output range was a maximum of 1.48 V on a 3.3V supply voltage, corresponding to a maximum 2.55 V swing at the photodiode. Time-varying output noise was measured to be 0.51 mV, rms, at 100 MHz, for a dynamic range of ~11.5 bits, rms. Circuit design details are presented, along with the results of electrical measurements and optical experiments with fast pulsed laser light sources at several wavelengths.