A Single-Channel 14b 500 MS/s Pipelined-SAR ADC with Reference Ripple Mitigation Techniques and Adaptive-Biased Floating Inverter Amplifier

Abstract

The accuracy and speed of the residue handover process are crucial in two-step architectures. Advanced residue amplifiers (RAs) [1]–[5] enable a fast residue handover operation in Pipelined ADCs but often necessitate calibrations. Furthermore, with a short acquisition time and a large capacitive DAC in high-resolution designs, it is challenging to ensure the reference voltage of the DAC is sufficiently settled before the amplification. Eventually, the reference buffer (RBUF) calls for a considerable power and/or area overhead. This work introduces an adaptive-biased floating inverter amplifier (ABFIA) as the RA in a single-channel 14b 500MS/s Pipelined-SAR (Pipe-SAR) ADC, reaching a 16x calibration-free gain in a short time. Further, by leveraging a Reference Ripple Cancellation (RRC)coarse SAR ADC and Reference Ripple Neutralization (RRN)assisted RBUF, it avoids large sizing multi-input-pair in the comparator and the stringent timing requirement in conventional RRN [6] and RRC [7] technique, respectively.