Abstract
We proposed a new and low cost design of time-to-digital converter (TDC) based on Vernier method using only one FPGA EPF10K30ATI144-3 with 1.3 ns timing resolution performance. Neither ECL (emitter-coupled logic) circuit nor high frequency clock was used in this design, which greatly reduced the complication and the power supply. We used two oscillators with slightly different frequencies to measure small time interval. All the time-to-digital converter functions were implemented on only one low-cost Altera FLEX II Family device. Our preliminary results showed: 1) Vernier TDC had a less than 1.3 ns timing resolution that met the demand for coincidence measurement for LYSO MicroPET. 2) No inacceptable degradation was observed in time resolution as of the number of the sliding jaw clock circulations was increased before coincidence. 3) Vernier TDC accomplished on FPGA had good stability with temperature. In a sum, we made a sufficient proof of high resolution and good stability of the proposed Vernier TDC design. Now, we are planning to achieve higher time resolution and higher stability by high-performance FPGA using this smart Vernier TDC method. And such simple design is being applied to our animal PET.
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