A Sampled-Data Approach to DC-DC Buck Converter Design

Abstract

This paper examines the design of digital compensators for high frequency switching dc-dc buck converters. While a high sampling frequency is desirable for digital controllers to minimize intersample effects and recover the performance of the analog compensator (e.g. regulation, robustness with respect input voltage and load fluctuations), finite wordlength effects (i.e. binary approximation/truncation) become more pronounced when faster sampling rates are used. High sampling rates are also accompanied by larger power consumption. When low sampling rates are used, (appropriate truncation algorithms) permit the use of fewer bits to represent compensator coefficients. This reduces final chip area, power consumption, and cost - all very important for application-specific integrated circuit (ASIC) applications. This, however, comes at the expense of performance degradation because of zero-order-hold (ZOH) phase lag and intersample effects. This is a fundamental limitation associated with the traditional two-step design procedure - analog-design followed by conversion-to-digital. While one can compensate for the effects of the ZOH/intersample behavior, direct discrete-time design approach is more systematic. It must be noted, however, that even a direct discrete-time design approach has fundamental limitations. This is because such an approach does not directly take into account intersample behavior. Because of this, the direct design approach may result in unnecessarily (conservatively) high sampling rates.