A review of FPGA-based design methodology and optimization techniques for efficient hardware realization of computation intensive algorithms

Abstract

Field programmable gate arrays (FPGAs) have emerged as platform of choice for efficient hardware realization of computation intensive algorithms because of their intrinsic parallelism and flexible architecture. However, to achieve high performance, FPGA must be supported by efficient design methodology and optimization techniques. In this paper, FPGA-based design methodology and optimization techniques that can be employed to obtain area, speed and power efficient circuits are reviewed and presented.