A Resource-Limited FPGA Accelerator for Deep Convolutional Neural Networks

Abstract

We present a new hardware architecture for deep convolutional neural networks for low cost field programmable logic array (FPGA). By using extensible parallel engine implementation of Winograd algorithm coupled with input and output line buffers, the proposed hardware architecture requires less hardware resources in FPGA. We describe the architectural design in detail and shows the implementation results in a resource limited FPGA device. From the experimental results, our proposed architecture requires less hardware resources in FPGA compared to other current FPGA implementations.