A Reinforcement Learning Based Adaptive Mutation for Cartesian Genetic Programming Applied to the Design of Combinational Logic Circuits

Abstract

The design of digital logic circuits involves transforming logical expressions into an electronic circuit seeking to minimize certain attributes such as the number of transistors. There are deterministic algorithms for this task, but they are limited to small problems. On the other hand metaheuristics can be used for solving this type of problem and Cartesian Genetic Programming (CGP) is widely adopted in the literature. In CGP, mutation is commonly the only operator for generating new candidate solutions. Thus, the performance of this metaheuristic is dependent on the proper choice of mutation and its parameters. Normally, CGP mutates the candidate solutions according to a uniform distribution. Thus, any modification has the same chance to occur. In order to improve the performance of CGP an adaptive mutation operator using an $\epsilon$-greedy strategy for bias the selection of gates is proposed here. The proposal is evaluated using problems of a benchmark from the literature. The results obtained indicate that the proposed adaptive mutation is promising and that its relative performance increases with the size of the problem.