Abstract

A reconfigurable systolic array is described. The concept centers on the direct mapping of a static data flow into hardware; each node (or group of nodes) of the data flow graph is replaced by a processing element (PE). Several PEs can be grouped together forming an optimal interconnection structure to process subgraphs. This architecture permits implementation of most algorithms that can be described using static data flow graphs. This class of algorithms encompasses most common signal processing applications. >

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