Abstract
A histogramming integrated circuit has been designed with 256 24-bit cells. The pipelined RAM-based architecture has been designed to give histogram capture rates of at least 8 MHz. The chip is capable of histogramming an entire 512*512 image with an 8-bit gray level in real time and is fully cascadable for increased histogram resolution or capacity. The RAM is accessible for random read/write operations through the 24-bit data and 8-bit address busses. Additional features include global thresholding, sequential read/clear, and a simple self-test on the RAM. The chip was designed using an integrated design system with a ramcell compiler and is being fabricated in a 2- mu m CMOS technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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