Abstract
In this paper, a radiation-hardened resistive random-access memory (RRAM)-based non-volatile (NV) latch with a dual-interlocked storage cell is proposed and analyzed. The single-event effects of the proposed NV latch are simulated and discussed. Simulations of the proposed element are based on a 0.18 μm complementary metal-oxide-semiconductor design kit for the peripheral circuit and the voltage threshold adaptive memristor model for the RRAM. The simulation results indicate that the injected charge to induce a single-event upset (SEU) of the proposed NV latch is above 4.5 pC. As compared to the traditional RRAM based NV latch, the proposed NV latch is relatively immune to an SEU. This immunity from the SEU originates from the redundant storage nodes and interlocked feedback mechanism. Moreover, the area overhead of the proposed NV latch (eight transistors in the core storage element) are much lower than other radiation-hardened technology, e.g. TMR or FERST.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
