Abstract

We study enhancement-mode n++-GaN/InAlN/GaN high electron mobility transistors (EHEMTs) by means of two-dimensional numerical device simulation. An introduction of a highly-doped GaN cap layer, which is recessed under the gate, was initially proposed for an improvement of the device performance by diminishing surface traps-related parasitic effects. Our new simulation results reveal that, unlikely to planar transistor structures, the extension of the gate depletion region with drain bias is kept restricted in the presence of a n++-GaN cap layer. This highly-scaled new device concept is very promising for ultra-high frequency performance.

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