Abstract
This paper describes an Application Specific Processor to be used as the central component for signal processing and general control tasks of a combined GPS/Loran-C/Omega/MLS navigation receiver. The processor uses vector registers to enhance throughput of signal processing applications, resulting in a single-cycle multiply-accumulate operation, without compromising scalar performance. To minimize design effort, the processor is built on top of a processor framework. Two frameworks are considered and the recently reported MOVE architecture is shown to be superior to a VLIW architecture. The processor is targeted at a 180,000 transistor, 1.6 μ CMOS sea-of-gates image and the clock frequency is projected to be 125 MHz.
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