A Practical DPA Countermeasure with BDD Architecture

Abstract

We propose a logic-level DPA countermeasure called Dual-rail Pre-charge circuit with Binary Decision Diagram architecture (DP-BDD). The proposed countermeasure has a dual-rail pre-charge logic style and can be implemented using CMOS standard cell libraries, which is the similar property to Wave Dynamic Differential Logic (WDDL). By using novel approaches, we can successfully reduce the early propagation effect, which is one of the main factors of DPA leakage of WDDL. DP-BDD is suited to implementation of S-boxes. In our implementations of the AES S-box, DP-BDD can reduce the maximum difference of transition timing at outputs of S-box to about 1/6.5 compared to that of WDDL without delay adjustment. Moreover, by applying simple delay adjustment to the inputs of the S-box, we can reduce it to about 1/85 of that without the adjustment. We consider DP-BDD is a practical and effective DPA countermeasure for implementation of S-boxes.