A power optimization method considering glitch reduction by gate sizing

Abstract

We propose a power optimization method considering glitch reduction by gate sizing. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the accuracy of statistical glitch estimation method and a device gate sizing algorithm that utilizes perturbations for escaping a bad local solution. The effect of our method is verified experimentally using 12 benchmark circuits with a 0.5 /spl mu/m standard cell library. Gate sizing reduces the number of glitch transitions by 38.2% on average and by 63.4% maximum. This results in the reduction of total transitions by 12.8% on average. When the circuits are optimized for power without delay constraints, the power dissipation is reduced by 7.4% on average and by 15.7% maximum further from the minimum-sized circuits.