Abstract
Side-channel Attack, such as simple power analysis and differential power analysis (DPA), is an efficient method to gather the key, which challenges the security of crypto chips. Side-channel Attack logs the power trace of the crypto chip and speculate the key by statistical analysis. To reduce the threat of power analysis attack, an innovative method based on random execution is proposed in this paper. In order to enhance ability against DPA, the method disorders the correspondence between power trace and operands by scrambling the data execution sequence randomly and dynamically. Experiments and verification are done on the Sakura-G FPGA platform. The results show that the key is not reveal after even 1 million power traces by adopting proposed method and only 1.12% slices overhead is introduced. Compared to unprotected chip, it increases more than 140× measure to disclosure.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
