Abstract
Heterogeneous integration of high-quality crystalline semiconductor materials and devices compatible with the back end of line (BEOL) CMOS wafers are fundamentally limited by two factors: (i) the lack of a crystalline growth surface and (ii) the <400 ° C thermal budget. Here, we demonstrate a platform for monolithic integration III-V devices directly on amorphous substrates at a growth temperature of 300 ° C by low temperature templated liquid phase (LT-TLP) method. Furthermore, we demonstrate that degenerately doped materials can also be directly grown at <400 °C via LT-TLP, establishing the building blocks for high performance back end devices.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
