Abstract
This paper presents a novel input/output interface circuit for field programmable gate array (FPGA) devices, which has high voltage tolerant and PCI compliant capabilities. In the proposed circuit, dynamic gate and N-well bias technology is used to eliminate gate-oxide overstress and Pad to output supply (Vcco) leakage current when FPGA devices operate with high voltage input, and to ensure that over-voltage and under-voltage at Pad is avoidable when FPGA devices connect with PCI devices. The proposed circuit can be used as an interface IP and had been successfully applied in a 200MHz SRAM-based FPGA device using both 2.5V and 3.3V MOS transistors in a 0.25um CMOS process with dual-oxide option.
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