A novel fabrication process of a silicon field emitter array with thermal oxide as a gate insulator

Abstract

We have successfully developed a fabrication process of a silicon field emitter array with a gate insulator formed by Si/sub 3/N/sub 4/ sidewall formation and subsequent thermal oxidation. This process overcomes some problems in the conventional fabrication, such as high etch rate, low breakdown field, and gate hole expansion arising from evaporation of gate oxide. Therefore, we could improve process stability and emission performance, and also reduce gate leakage current. The optimum process conditions were determined by process simulations using SUPREM-4. The turn-on voltage of the fabricated field emitters was approximately 38 V. An anode current of 0.1 /spl mu/A (1 /spl mu/A) per tip was measured for a 625-tip array at the gate bias of 80 V (100 V), and the gate current was less than 0.3% of the anode current at those emission levels. >