A novel associative approach for fault-tolerant MOS RAMs

Abstract

A novel associative iterative approach providing unique advantages is developed to increase yield of large capacity, 16K bit-1M bit, semiconductor random access memories. The circuit implementation has minimum effect on performance and on the original design of the memory. The increase in access time and power dissipation is less than 2 and 0.6 percent, respectively. The flexibility of this concept allows for organization of redundant elements in blocks, rows, columns, clusters, or bits and to locate the redundancy anywhere on the chip. A wide range of programmable elements, e.g., fusable links, laser programmable cells, and content addressable memory units, are applicable. The amount of spare elements can be optimized to achieve a maximum effective yield of as much as 85 percent. The increase in active circuit area is a function of defect density and memory capacity. The redundancy control and spare memories can be added to memories as modules without modifications of the original designs. The circuits discussed here are for CMOS/SOS radiation hardened application; the concepts, however, can be applied to bulk silicon MOS technologies as well.