A nonscan DFT method for controllers to provide complete fault efficiency

Abstract

AbstractIn this paper, we propose a method for non‐scan design for testability of controllers that are logically synthesized from a finite state machine (FSM), which provides complete fault efficiency. In the previously used scan method, a test pattern for the combinational circuits of a controller was generated to achieve complete fault efficiency and was applied by using a scan flip‐flop. However, in the scan method, the test sequence becomes large and various problems prevent the test from being performed at the actual operating speed. In this paper, the test pattern of the combinational circuits of the controller does not use scan flip‐flops, but instead uses the state transitions of an FSM. The proposed method allows performance of the test at the actual operating speed of the circuit, thus reducing the testing time compared to the conventional methods. Moreover, experimental results using benchmarks show that the area overhead is small. © 2002 Wiley Periodicals, Inc. Syst Comp Jpn, 33(5): 64–75, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.1128