A new statistics-based online baseline restorer (SOBLR) for a high count-rate fully digital system

Abstract

This study is to develop a novel, accurate, real-time digital baseline restorer using online statistical processing for a high count-rate digital system such as positron emission tomography (PET). In high count-rate nuclear instrumentation applications, analog signals are DC-coupled for better performance. However, the detectors, pre-amplifiers and other front-end electronics would cause a signal baseline drift in a DC-coupling system, which will downgrade the performance of energy resolution and position accuracy. Event pileups normally exist in a high-count rate system and the baseline drift will create errors in the event pileup-correction. Hence, a baseline restorer (BLR) is required in a high count-rate system to remove the DC drift ahead of the pileup correction. Many methods have been reported for BLR from classic analog methods to digital filter solutions. However a single channel BLR with analog method can only work under 500KCPS count-rate, and normally a CMOS front-end ASIC is required for the application involved hundreds BLR such as a PET camera. We have developed a simple statistics-based online baseline restorer (SOBLR) for a high count-rate fully digital system, and hundreds SOBLRs can be implemented in one field-programmable gate array (FPGA). In this method, we acquire additional samples, excluding the real gamma pulses, from the existing free-running ADC in the digital system, and perform an online statistical processing to generate a baseline value. This baseline value will be subtracted from the digitized waveform to retrieve its original pulse with zero-baseline drift. This method can self-track the baseline without a micro-controller involved. The circuit consists of two digital counter/timers, one comparator, one register and one subtraction unit. Simulation shows a single channel works at 30MCPS count-rate with pileup condition. 336 baseline restorer circuits have been implemented in FPGA for our new fully digital PET system.