A New Spatiotemporal CMOS Imager With Analog Accumulation Capability for Nanosecond Low-Power Pulse Detections

Abstract

High-speed cameras use the interesting performances of CMOS imagers that offer advantages in on-chip functionalities, system power reduction, cost, and miniaturization. The FAst MOS Imager (FAMOSI) project consists in reproducing the streak camera functionality with a CMOS imager. In this paper, a new imager called FAMOSI 2, which implements an electronic shutter and analog accumulation capabilities inside the pixel, is presented. With this kind of pixel and the new architecture for controlling the integration, FAMOSI 2 can work in repetitive mode for low light power and in single shot mode for higher light power. This repetitive mode utilizes an analog accumulation to improve the sensitivity of the system with a standard n-well/p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub </sub> photodiode. The characterization has been realized in single shot mode to optimize the accumulation mode. The prototype has been fabricated in the Austriamicrosystems 0.35-mum CMOS process. The chip is composed of 64 columns times 64 rows of pixels. The pixels have a size of 20 mum times 20 mum and a fill factor of 47%