A New Method of True Random Number Generation based on Galois Ring Oscillator with Event Sampling Architecture in FPGA

Abstract

This paper proposes a new entropy extraction mechanism from clock jitter for the implementation of a true random number generator (TRNG) in a field programmable gate array (FPGA). Different with conventional clock sampling architecture, where a jittery signal is sampled by a regular clock signal, we use the jittery clock signal generated by Galois ring oscillator (GARO) to sample the regular clocks that are generated by normal phase locking loop (PLL) of FPGA. This sampling architecture is hereafter called as event sampling architecture. To guarantee every sampled bit has maximum entropy value, the regular clock signal is routed into a tapped delay line (TDL) forming a multi-phase clock signal before it is sampled for exclusive OR (XOR) operation. A prototype of such a TRNG is implemented in a Xilinx Artix-7 FPGA. The generation rate, the randomness of the bit sequence, as well as its robustness to ambient temperature are evaluated in detail. Comparing with the similar TRNG implementation but using the clock sampling architecture, the proposed TRNG can increase the generation bit rate by 1.33 times, while the logic resource consumption is greatly reduced (saving 33% of the look up tables and 81% of the flip-flops). A comparison with various prior TRNG designs in terms of category, logic resource usage, and generation rate demonstrate that the proposed method has the advantage of high rate of generation rate to logic resources. Therefore, it is more suitable for the generation of high-speed true random numbers, which is especially important for applications in current high-speed quantum key distribution systems.