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Abstract
Full adder circuits are basic digital used in almost all multiplier architectures. Consequently, they serve as the fundamental building blocks in many digital signal or image processing systems. Different logic styles are employed in the design of full adder circuits, with the hybrid logic style being the most recent method for implementing low-power full adders. A hybrid full adder primarily relies on the XOR-XNOR module. This module greatly affects the performance of any hybrid full adder in terms of driving capability, power consumption, delay, and area. This paper proposes a new design of a hybrid full adder by introducing the CCGDI technique-based XOR-XNOR module. Simulation results demonstrate that the proposed CCGDI-based hybrid full adder architecture, constructed with a ratioless 12 transistors, consumes 9.48 µw of power and has a latency of 34.23 ps. A comparison with other state-of-the-art structures of hybrid full adders reveals a significant improvement in PDP (power-delay product) and driving capability.
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