Abstract
The next generation of high level ASIC design systems will be able to transform an algorithmic behavioral description on register transfer (RT) level automatically to fabrication data. However, in ASIC design, there are several important levels higher than RT. In this paper we will motivate a formal, computer-aided approach to describe chips on the next higher level - the system level. Here, chips are specified in a much more abstract way than on RT level. We also have to care about modeling of incomplete and inaccurate information. Therefore, we will introduce a new architecture description language as a base to model a chip on system level and an interactive architecture compiler to transform this system level description to a RT-algorithm.
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