Abstract
The design, simulations, and tests of a 16-channel chip for solid-state detectors are presented. The chip produces sparsified pulse trains for both linear (pulse height) and timing (relative to an external reference) and allows the use of one of two internal charge sensitive amplifiers or an external amplifier. A shaper and peak detector are implemented in the linear branch and a pseudo-constant fraction discriminator and time-to-voltage converter are implemented in the logic/timing branch. The internal plus external gain options and the preparation of both pulse height and timing pulse trains suitable for pipeline ADCs, makes the chip suitable for a wide variety of applications. The chip was fabricated in the AMI 0.5 μm n-well (C5N) process available through MOS implementation services (MOSIS).
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