A Multi-Bit Quantization Delta-Sigma ADC using Global Chopper

Abstract

In this paper a multi-bit quantization Delta-Sigma ADC with global chopper technology is presented. Four-order 4-bit quantization modulator with improved Cascaded Integrators Feed-Forward (CIFF) architecture is adopted in order to reduce the input branch of adder and use relatively large coefficients, which minimize branch load and improve the signal to noise and distortion ratio (SNDR) of the modulator. Decimation filter is implemented with five-stage cascaded integrator comb (CIC) filter. The global chopper technique cooperates with the modulator and the CIC filter to reduce the dc offset in the overall system. Implemented in 0.35μm CMOS technology, simulation results show that with a sampling frequency of 38.4 kHz, the signal bandwidth can be adjusted from 75 to 1.2 kHz. The SNDR of the modulator can be as high as 125.8dB. The overall ADC achieves the effective number of bits (ENOB) is 20.4 bits, and the harmonic distortion is under −130dB.